Reduced Clock Allocation Network for On-Chip Compression Format in VLSI Design
نویسنده
چکیده
Now-a-days power dissipation is a vital subject in elevated presentation digital routes, because the amount of transistors has increased significantly. Several methods have been planned to decrease the switching activity. This paper presents a new examination data compression technique based on a Huffman compression code that uses a viterbi decoder. Huffmann compression is used to compress the data in the clock tree method. In the proposed system, the power and clock skew are reduced by using the huffman compression technique. Experimental result indicates the flexibility and efficiency of the proposed method. This method simulated in modelsim software.
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