Watermarking Techniques for Electronic Circuit Design

Enforcing copyright laws aimed at intellectual property protection of electronic design is generally considered a hard task. The difficulty is in discovering infringements effectively and proving them as such in a court of law. While reverse engineering is a widely used and legal tool to extract schematics from fabricated integrated circuits, determining that a given circuitry is trivially derived from a patented technique or method is very hard, often impossible, in a reasonable amount of time. Furthermore, forensic analysis of fabricated chips is usually so complex that its application to large collections of commercial products is usually prohibitive. Watermarking is one of several techniques available today to deter copyright infringement in electronic systems. The technique consists of implanting indelible stamps in the circuit’s inner structure, while not disrupting its functionality or significantly degrading its performance. In this paper a series of methods is proposed for the creation of watermarks at several stages of the design cycle, from high-level design to layout. Algorithms are described for implanting robust watermarks to minimize the overhead and, ultimately, to reduce the impact on performance. Detection methods have also been discussed in the presence of infringement. The resilience of the methods in several tampering regimes has been estimated.