A 69dB SNDR, 25MHz BW, 800MS/s Continuous-Time Bandpass ΔΣ ADC Using DAC Duty Cycle Control for Low Power and Reconfigurability

A new power-efficient, reconfigurable, 6-order continuous-time bandpass delta-sigma modulator architecture is presented. A new duty-cycle-controlled DAC halves the number of DACs in the modulator, and also enables the center frequency to be reconfigurable. A prototype 800MS/s modulator achieves 69dB SNDR with a 25MHz bandwidth at a 200MHz IF. The center frequency can be varied from 180MHz to 220MHz. The 65nm CMOS prototype consumes 35mW and occupies a die area of 0.25mm. Introduction Despite recent improvements [1-3] in the power efficiency of continuous-time bandpass ΔΣ modulators (CTBPDSMs), CTBPDSMs still consume more power than other kinds of data converters and introduce design challenges. Furthermore, although a CTBPDSM with a reconfigurable center frequency could potentially eliminate analog blocks in the receiver chain and make the receiver more flexible [2], existing reconfiguration techniques are complicated. Another desirable characteristic is a signal transfer function (STF) with modest input signal filtering for robustness against out-of-band interferers, which would otherwise significantly decrease the dynamic range. We introduce a new architecture that is both simple and reconfigurable, through a new duty-cycle-controlled feedback DAC scheme. A single, duty-cycle-controlled DAC replaces the conventional pair of return-to-zero (RZ) and half-clock-delayed RZ (HZ) DACs that are usually required for each resonator. This new architecture enables input signal filtering without peaking in the STF. Thanks to the duty-cycle controlled DAC, the center frequency is easily reconfigurable. Along with these new features, this CTBPDSM has the best figure-of-merit of any CTBPDSM with an active resonator. Duty-cycle-controlled DAC A flexible modulator center frequency requires adjustment of both the feedback and/or feedforward coefficients, as well as modification of the resonance frequency of resonators. [4] transforms a discrete-time bandpass ΔΣ modulator (DTBPDSM) to a CTBPDSM with RZ and HZ DACs. Unlike other approaches, this transformation is not limited to the condition that the center frequency Fc is Fs/4, and can be used for the transformation of DTBPDSMs with any Fc between DC and Fs/2. If the resonator is tunable then from analysis of the loop impulse response, the modulator can operate with any Fc by changing the amplitudes of the RZ and HZ pulses (Fig. 1). Different combinations of RZ and HZ DAC amplitudes (a1,b1) and (a2,b2) enable different center frequencies, Fc1 and Fc2 since they lead to the appropriate sampled loop impulse response required for different values of Fc. Therefore, reconfiguration of Fc can be achieved by adjusting the RZ and HZ DAC currents, but conventionally this requires both RZ and HZ DACs for each resonator. A significant drawback with this conventional approach to frequency reconfiguration is that it requires both an RZ and an HZ feedback DAC for each resonator. This prevents the use of the new architecture in [3] that halves the number of feedback DACs. [3] eliminates one feedback DAC per resonator thereby significantly reducing power consumption, thermal noise and silicon area. However, the scheme in [3] requires a feedforward path to remove one DAC and this has the disadvantage of causing STF peaking. Furthermore, reconfiguration of Fc is not possible because the approximation made to remove another feedback DAC is only valid for Fc =Fs/4. To overcome these limitations, we introduce a single variable-duty-cycle non-return-to-zero (NRZ) DAC to replace the combination of the RZ and HZ DACs, without affecting the original STF with filtering. Here adjustment of the duty cycle allows a single DAC to emulate the combination of HZ and RZ DACs in a CTBPDSM since both the pulse width and pulse amplitude convey information. Fig. 2(a) shows the waveform resulting from the combination of RZ and HZ pulses with RZ and HZ DAC amplitudes of ‘a’ and ‘b’. The waveform of the new duty-cycle controlled DAC in Fig. 2(b) is NRZ, and has a constant amplitude ‘c’, and the duty cycle is no longer 50%. Thanks to the variable duty cycle, the waveform has information in the amplitude ‘c’ and the duty cycle ‘α’, while the conventional combination of RZ and HZ DACs only has information in the amplitude of the two pulses. Therefore, the duty-cycle controlled DAC waveform of Fig. 2(b) is made equivalent to that of Fig. 2(a) in one clock period of a CTBPDSM by choosing ‘c’ and ‘α’. It can be easily shown that the sampled loop impulse response of this duty-cycle-controlled DAC, plus resonator, in a CTBPDSM is exactly the same as that for the two DAC system. By adjusting the duty cycle, this new DAC easily facilitates a CTBPDSM with Fc≠Fs/4. The advantage of the duty-cycle-controlled DAC scheme is that it has constant amplitude and can be implemented with a single DAC. This significantly reduces the power consumption and thermal noise of the DACs, and simplifies the modulator architecture. The new DAC scheme halves the total number of DACs without any detrimental modification of the architecture (such as additional feedforward paths). In this way the Fig. 1 Center frequency tuning by adjusting the amplitude of RZ and HZ DAC pulses. 5-2