Low-power readout circuit for quanta image sensors

Introduction: The ‘quanta image sensor (QIS)’ is being explored as a possible next-generation solid-state imaging technology to address issues with ‘sub-diffraction-limit (SDL)’ pixel sizes in the ‘CMOS image sensor (CIS)’ [1–3]. In the QIS concept, individual photoelectrons are counted by specialised SDL pixels termed ‘jots’, and the output of each jot is binary in nature. In addition to spatial oversampling, the fields are readout at high-speed (e.g. hundreds of fields per second) providing a sort of temporal oversampling. This approach provides an unprecedented level of flexibility in the subsequent image formation process, leading to interesting new applications like the ‘digital film sensor’. One of the QIS challenges is the implementation of high-speed and low-power sense amplifiers (SAs) at the bottom of every column in the QIS to convert a 1 mV p–p signal to digital levels. Thus, unlike the programmable gain amplifier and 12–14 b per column analogue-digital converter (ADC) found in conventional CIS devices [4], the QIS requires only the gain and a single comparator (1 b ADC). However, the QIS readout circuitry operates at frequencies that are more than at least 10–100 times higher than the conventional CIS and the number of columns may also be 10 times larger. Thus, both speed and power consumption is critical. Even for transitional, lower scan rate, binary image sensors [5, 6], the power dissipation (estimated at 100 μW per column) would be prohibitive if scaled up to 10 times more columns operating 10–100 times faster. In this Letter, a pathfinder circuit for QIS readout is presented that can resolve a 0.5 mV input difference, operates at 1 MHz and consumes 2 μW of power per column, a 50-fold improvement from the state of the art.