Ultra low power TFET-based circuits

University Institut Supérieur d’Electronique de Paris (ISEP) – Paris, France Description: Today the circuits dissipate a lot of power without offering performance increase from one technological node to another. It is therefore logical to investigate other solutions than the classical CMOS ones in the attempt to reduce the power consumption. In this context the tunneling FET (TFET) is seen as a possible replacement for CMOS device. While a lot of effort has seen performed to the development of this new technology at the device level, less was done at the circuit level. The few reports in the literature on TFET circuits describe mostly the design of TFET SRAM cells[3] Even so, much has to be done for the improvement of these new cells. Our group has hands-on experience in this field and proposed already some solutions for device performance improvement 7,8 or for solving critical issues at the circuit level 9. Having in mind the continuity of our research activity in this field, two short stages are open at ISEP for the estimation of the performance of these new emerging cells. The work is going to be carried out in the framework of our research team and could offer the possibility to the students to evolve and develop their skills in the field of circuit design. If successful results are obtained, it could represent an opening for a Ph.D. position.