Bubbles Can Make Self-Timed Pipelines Fastt

نویسندگان

  • MARK R. GREENSTREET
  • KENNETH STEIGLITZ
چکیده

We explore the practical limits on throughput imposed by timing in a long, self-timed, circulating pipeline (ring). We consider models with both fixed and random delays and derive exact results for pipelines where these delays are fixed or exponentially distributed random variables. We also give relationships that provide upper and lower bounds on throughput for any pipeline where the delays are independent random variables. In each of these cases, we show that the asymptotic processor utilization is independent of the length of the pipeline; thus, linear speedup is achieved. We present conditions under which this utilization approaches 100%.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings

Asynchronous pipelines control the flow of tokens through a sequence of logical stages based on the status of local completion detectors. As in a synchronously clocked circuit, the design of self-timed pipelines can trade off between achieving low latency and high throughput. However, there are more degrees of freedom because of the variances in specific latch and function block styles, and the...

متن کامل

Interacting Self-Timed Pipelines and Elementary Coupling Control Modules

SUMMARY The self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electromagnetic interference. These basic features of the STP have been proven by the development of self-timed data-driven multimedia processors, D...

متن کامل

Self-timed 1-D ICT processor

This paper describes a LSI implementation of 1-D order-8 Integer Cosine Transform (ICT) which can calculate either forward or reverse transformation. It is a standard-cell based design using 0.7μm CMOS SLP DLM process. The chip’s performance is maximized with the fast computation algorithm and self-timed circuit technique. It consists of eight parallel selftimed pipelines. Each self-timed block...

متن کامل

Logic depth and power consumption in self-timed circuits: A case-study

In this paper the non-linear relationship between power consumption and throughput in two-phase self-timed (ST) pipelines is demonstrated. This effect is explained by connecting two well-known phenomena: first, the adaptation between instantaneous logic depth and data rate, an attribute inherent to two-phase selftimed pipelines; and second, the increment of data path power consumption with the ...

متن کامل

Dynamic Self-timed Logic Structures

The realization of fast datapaths in signal processing environments requires fastest logic styles with synchronous behavior. This paper presents a systematic method which efficiently combines improvements on algorithm and logic level. Thus, the design of power efficient, fast and synchronous pipelines is possible. To reduce the power consumption of dynamic logic, we show methods for single-rail...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1990