Efficient VLSI Architectures for Error-Correcting Coding A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA BY

This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density ParityCheck (LDPC) codes, and Reed-Solomon codes. A systematic low-complexity bit-parallel finite field multiplier design approach is proposed. This design approach is applicable to GF (2m) constructed by arbitrary irreducible polynomials. It effectively exploits the spatial correlation in the bit-parallel finite field multiplication to reduce the hardware complexity. A systematic low-complexity design approach for modified bit-parallel multiplier that is desirable for GF (2m) constructed by high-Hamming weight irreducible polynomials is also proposed. For the hardware implementation of LDPC code decoder, the finite precision analysis is performed to develop a quantization scheme considering the tradeoff between hardware complexity and LDPC code error-correcting capability. A joint (3, k)-regular LDPC code and codec design approach is proposed to develop good (3, k)-regular LDPC codes that exactly fit to high-speed partly parallel decoder and low-complexity encoder implementations. A modified joint design approach is proposed to further reduce the decoder hardware complexity for those high-rate (3, k)-regular LDPC codes applied to silicon area critical applications. To demonstrate this joint design methodology, an FPGA (Field Programmable Gate Arrays) implementation of a (3, 6)-regular LDPC partly parallel decoder is realized using Xilinx virtex-E device. This decoder can achieve upto 54Mbps symbol decoding throughput and BER of 10−6 at 2dB over AWGN channel. Generalized Low-Density (GLD) Parity-Check has been proposed as an alternative to the product code. This thesis considers the practical GLD codec VLSI design. An approach is proposed to reduce the GLD encoding complexity, which can be effectively implemented using hardware/software codesign. It has been shown that Max-Log-MAP algorithm is a promising candidate decoding scheme for practical GLD coding systems by developing several techniques to reduce the GLD decoding complexity. A Berlekamp-Massey algorithm transformation is performed for high-speed errorsand-erasures RS decoder implementation. A regular hardware architecture is presented to implement the reformulated Berlekamp-Massey algorithm, and an operation scheduling scheme is proposed to reduce the hardware complexity without loss of speed.