Implementing a New Architecture of Wavelet Packet Transform on FPGA

In this paper, a new design of the Discrete Wavelet Packet Transform with efficient hardware acceleration is implemented. This design works based on the word serial pipeline architecture and the parallel filter processing. For accelerating in the Discrete Wavelet Packet Transform, a high-pass filter and a low-pass filter are used concurrently in each level. Using parallel filters makes possible that this design works two times faster than the design introduced in [10]. This architecture is implemented using internal multipliers of the FPGA and results of these implementations for the different filter lengths are presented. The AT 2 figure of merit for the implemented architecture relative to the architecture presented in [10] is smaller than 0.5. This high speed architecture is suitable for on-line applications and can be implemented for the Direct Wavelet Packet Transform with any levels of tree. Key-Words: Tree structure, WPT, memory, processor, implementation, CLB.