A Low-Cost Stimulus Design for Linearity Test in SAR ADCs

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-μm CMOS technology and the measured differential nonlinearity (DNL) error is between −0.386 and 0.281 LSB at 1-MS/s. key words: analog-to-digital converter (ADC), design for testability (DFT), pattern generator (PG), output response analyzer (ORA)