A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's

We report an SRAM with a 90% reduction of activeleakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells, the wordline voltage is controlled so that it is always lower than the supply voltage in the proposed SRAM, with a self-alignment timing generator. The additional area overhead of the timing generator is 3.5%. key words: active leakage, low power, SRAM