Continuous-time Feedback in Floating-gate Mos Circuits

We present the negativeand positive-feedback circuit congurations of continuous-time oating-gate MOS circuits. We start by reviewing the dynamics of our pFET and nFET single-transistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circuits with one oating-gate synapse, including data from nFET and pFET synapses. We then show examples of competitive and cooperative behavior in multiple-synapse circuits. We present experimental data from circuits fabricated in the 2 m nwell Orbit CMOS process available through MOSIS. One of our fundamental requirements of a silicon synapse [1-3] is that the synapse locally implements a learning rule for modifying the weight on the oating gate; in our case, the form of this rule depends on how various error signals are fed back to the oating gate synapse. The nature of this feedback is the focus of this paper. The usefulness of negative or positive feedback depends on the application; Hebbian learning, for example, is a case of destabilizing positive feedback. This paper considers the behaviors that emerge when single-transistor synapses are coupled together to form various continuous-time learning networks. Our purpose is to understand the dynamics of the learning mechanisms naturally available in oating-gate MOS circuits. We present a deeper discussion of oating-gate dynamics elsewhere [2]. We present experimental data from circuits fabricated in the 2 m nwell Orbit CMOS process available through MOSIS. We have characterized and modeled the dynamics of nFET and pFET single-transistor synapses operating in continuous-time circuits. This work builds the framework to consider oating-gate circuits not only as memory elements, but as continuous-time circuit elements computing at several timescales. 1. MODEL OF SINGLE-TRANSISTOR SYNAPSES Figure 1 shows circuit diagrams of the nFET and pFET synapses. The starting point is our models of the channel current, electron-tunneling current, and hot-electron{ injection current of nFET and pFET oating-gate synapses [1, 2, 3]. For this paper, we de ne the weight of the synapse, W , as the source current normalized by a bias current, Iso. Often we de ne W without the changes in the oating-gate voltage due input signals at shorter timescales than these Figure 1: (a) Circuit diagram and small-signal model of the nFET single-transistor synapse with its source connected to ground. (b) Circuit diagram and small-signal model of the pFET single-transistor synapse with its source connected to Vdd. For our discussion, we will assume non-negligable levels of electron-tunneling and hot-electron-injection current in these nFET and pFET transistors. adaptation behaviors [2]. For this paper, we will only model that the input (Vin) capacitively couples to Vfg, and that the input will change instantanously the oating-gate or drain voltages depending upon the particular circuit. We model the weight dynamics of an nFET synapse as UTCT Itun0 dW dt = UTC2W Itun0 dVd dt +W 1 UT nVx W 1+ e Vd=Vinj ; (1) and we model the weight dynamics of a pFET synapse as UTCT Itun0 dW dt = UTC2W Itun0 dVd dt +W 1+ UT pVx W 1+ e Vd=Vinj : (2) We de ne CT as the total amount of capacitance connected to the oating gate, Vx as a tunneling parameter related to the quiescent tunneling and oating-gate voltages, Vinj as an injection parameter related to the quiescent drain and oating-gate voltages, Itun0 as the quiescent tunneling and injection current, which is primarily dependant upon the tunneling voltage and power-supply voltage, as 1 UT Vinj , and C2 as the capacitance between oating gate and drain (which is not explicitly drawn for clarity). We assume that all the oating-gate devices are matched. A typical nFET value of is 0.70, and a typical pFET value of is 0:90; both values are consistent with typical values of Vinj . For our operating conditions, a typical value of Vx is 1V with the 42nm oxide used in the 2.0 m Orbit process. 0-7803-4455-3/98/$10.00 (c) 1998 IEEE 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -1 -0.5 0 0.5 1 Weight (W1) S-D pFET synapse nFET synapse pFET synapse