Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier

In this paper we propose a modified probabilistic estimation bias (PEB) formula for fixed-width radix-4 Booth multiplier. The modified PEB formula estimates the same compensation value as the existing PEB formula without rounding operation. A bias circuit based on modified PEB formula generates one less carry-bit and involves less logic resources than the existing PEB circuit. The partial product array (PPA) of existing PEB multiplier uses partial product bit as guard bit for sign extension. This is not an efficient approach as extra half-adders (HAs) are required to accumulate these sign extension bits. We have considered PPA of conventional modified Booth encoded (MBE) multiplier where logic ’1’ is used as guard bit for sign extension. Logic ’1’ in the PPA helps to replace HA with a NOT-gate in the adder design. Based on the proposed scheme, we have derived an efficient adder design for PEB radix-4 Booth multiplier. Compared with the adder design of existing PEB multiplier, the proposed adder involves less logic resources and less critical path delay (CPD), and calculates the same compensation value. ASIC synthesis result shows that the proposed PEB radix-4 Booth-multiplier of sizes n = 8, 10, 12 and 16, respectively, involve 18%, 19%, 16%, 13% less ADP, and 12%, 16%, 11%, 12% less power consumption than the existing PEB multiplier. We have shown that an IP cell based on proposed fixwed-width radix-4 Booth multiplier involves 11.3% less ADP and consumes nearly 7.6% less power than an IP cell based on the existing PEB-based fixed-width multiplier on average for different inner-product sizes. The proposed multiplier is, therefore, an useful component to develop high-performance systems for digital signal processing (DSP) applications.