Supporting Information: Holey Silicon as efficient thermoelectric material

1. Holey Silicon fabrication The HS ribbons used for transport measurements are patterned by optical lithography and then released from SOI substrate (Soitec Inc.) by hydrofluoric acid vapor etching. The SOI wafer consists 100 nm device layer (<100>, 14-22 Ω·cm, phosphorus doped) with 200 nm buried oxide layer. Holey structure is fabricated by DRIE through thin chromium mask (~5 nm) converted from NSL or BCP pattern. Figure S1 shows the schematic of detailed fabrication of 350 nm and 140 nm pitch HS ribbons. 350 nm and 140 nm polystyrene spheres (Bangs laboratories, Inc.) are 1:4 diluted with de-ionized water and subjected to 2 min sonication before coating to insure homogeneous sphere suspension. The substrate is cleaned with piranha for 10 mins and rinsed with de-ionized water followed by N 2 blow-dry. Polystyrene spheres are self-assembled into hexagonal monolayer film via a dip coating process at speed ~4 μm/s in a customized dip coater equipped with isolating shield to prevent disturbing from air flow. Throughout the assembly process, line defects and point defects are sometimes observed mostly due to the non-uniformity of sphere size. Weak oxygen plasma (20 W at ~300 mtorr in the Technics PEII-A plasma system) is then used to etch polystyrene sphere until the desired spacing is obtained. 5 nm chromium film, served as silicon etching