Multi-controller reconfiguration system for FPGAs

Adaptivity is one of the most critical issues related to System-on-Chip (SoC) design. In order to be runtime adaptive, SoC have to take into account changes related to user preferences and environment at runtime. Dynamically reconfigurable SoC, such as those implemented on Field Programmable Gate Arrays (FPGAs), are a good solution for runtime adaptivity. Dynamic reconfiguration allows FPGAs to modify their functionality at runtime. Partial Dynamic Reconfiguration (PDR) has the potential of reconfiguring only some regions of the FPGA without disturbing the operation of the rest of the system, which decreases the impact of the reconfiguration time on the system performance, compared to the full reconfiguration. As the complexity of the reconfigurable SoC is increasing day after day, their reconfiguration control becomes more and more complex. In this case, using a single controller that controls the whole system might lead to a very complex design which is difficult to explore and to test. In this paper, we propose an approach that aims to decrease this complexity by dividing it into sub-modules. This approach is based on a multi-controller solution for the reconfiguration control of a partially reconfigurable system. Each controller controls the reconfiguration of a part of the system. Communicating together, the controllers insure the reconfiguration control of the whole system.