FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials

The efficient design of digit-serial multipliers for special binary composite fields, F2nm where gcd(n, m) 1⁄4 1, is presented. These composite fields can be constructed via an irreducible pentanomial of degree nm but not an irreducible trinomial of degree nm. The conventional construction method for such digit-serial multipliers is to exploit the simplicity of pentanomials to obtain efficent linear feedback shift registers together with AND–XOR arrays. In this approach, these binary fields are constructed via irreducible trinomials of degree m with respect to F2n which in turn are also constructed via an irreducible trinomial (Hybrid I) or pentanomial (Hybrid II) over F2. The bit-serial structure to the tower field and applying the bit-parallel structure to the ground field are applied to obtain the hybrid architecture. Three kinds of multipliers (conventional, Hybrid I and Hybrid II) are implemented using the same FPGA device. Since at least one level is constructed via a trinomial instead of a pentanomial, the hybrid multipliers are 10–33% more efficient than the conventional ones according to the post-place-and-route-timing analysis via Xilinx-ISE 7.1.