Process-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling

Process-variation induced skew has become one of the major contributors to the clock-skew in advanced technologies. Since process-variation induced skew is roughly proportional to clock-delay, it is preferable to design zero-skew clock-trees and have minimum clock-delay to reduce both unintentional and process-variation induced skews. In this paper, we propose a zero-skew buffered clock-tree synthesis flow and a novel algorithm that enables clock-tree optimization throughout the full zero-skew design-space by considering simultaneous buffer-insertion, buffer-sizing, and wire-sizing. Our algorithm can also utilize useful-skew and bounded-skew constraints to allow more aggrressive optimization. Extensive experimental results show that for an industrial clock-tree with 3101 sink nodes, our algorithm achieves up to 45X clock-delay improvement and up to 23% power reduction compared with its initial routing and provides process-variation, clock-delay, and power trade-offs in 16 minutes on a 1.2GHz Pentium IV PC.