A +-5-V CMOS Analog Multiplier
نویسندگان
چکیده
A four-quadrant CMOS analog multiplier is presented. The device is nominafly biased with +5-V supplies, has identicaf full-scafe single-ended x and y inputs of +4 V, and exhibits less than 0.5 percent Manuscript received March 1, 1987; revised July 18, 1987. The authors are with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128. IEEE Log Number 8716852. + I–— ————_—
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