Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell
نویسندگان
چکیده
In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and analyzed a 32 kb 1-port SRAM using 45 nm CMOS technology. The six-transistor SRAM cell size is 1.25 μm 2 . Evaluation shows that the standby current of 32 kb SRAM is 1.2 μA at 1.2 V and room temperature. It was reduced to 7.5% of the conventional SRAM.
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