Design of Reconfigurable Fft Processor Using Vedic Multiplier

The Fast Fourier Transform (FFT) is most widely used in DSP such as imaging, signal processing, frequency communication, applied wireless system. In this paper, a reconfigurable DIT8 point FFT design using Vedic multiplier with small area and low power is presented. Urdhava Triyakbhyam algorithm, an ancient Vedic Indian Mathematics sutra, is utilized to achieve high throughput. In the proposed architecture, the 8x8 bit multiplication operation is fragmented reconfigurable FFT modules. The 8x8 multiplication modules are implemented using small 2x2bit multipliers. Reconfigurability is provided in run time for attaining power optimization. The reconfigurable 8 point DITFFT with high through put has been designed, optimized and implemented on an Spartan. This reconfigurable 8 point DIT-FFT is having the high speed and small area as compared to the conventional DIT-FFT.