Verifying a Static RAM Design by Logic Simulation

A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system speciication will produce a particular response to a sequence of simulation commands. Three-valued modeling, where the third state X indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete veriication. As an extreme case, an N-bit random-access memory can be veriied by simulating just O(N log N) patterns. The technique has been applied to a CMOS static RAM design using the COSMOS switch-level simulator. This approach to veriication is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal veriication.