Effects of static and pulsed negative bias temperature stressing on lifetime in p-channel power VDMOSFETs

Threshold voltage shifts associated with negative gate bias temperature instability in p-channel power VDMOSFETs under the static and pulsed stress conditions are analysed in terms of the effects on device lifetime. The pulsed bias stressing is found to cause less significant threshold voltage shifts in comparison with those caused by the static stressing, which is ascribed to the effects of dynamic recovery and shorter actual stress time associated with pulsed bias conditions. Accordingly, pulsed gate bias conditions provide much longer device lifetime than the static ones, which is shown by individual use of the 1/V G and 1/T models for extrapolation to normal operation voltage and temperature, respectively, as well as by combined use of both models for a double extrapolation successively along both voltage and temperature axes. A double extrapolation approach is shown to allow for construction of the surface area representing the lifetime values corresponding to a full range of device operating voltages and