Comparison of 90nm and 65nm Logic Synthesis of a SAD Configurable VLSI Architecture
نویسندگان
چکیده
This paper evaluates the impact of the technology node on the area, performance and power consumption of a configurable VLSI architecture for Sum of Absolutes Differences (SAD). Such architecture may be configured to take benefit from pel decimation, trading off quality for energy. The proposed architecture was synthesized for 90nm and 65nm technologies assuming both nominal and Low-Vdd/High-Vt (LH) cases. Results showed that pel decimation itself is responsible for up to 60% of energy efficiency with a negligible area and power overhead with respect to a non-configurable reference SAD architecture. Our best result, using pel decimation 4:1 in 65nm/LH spends only 2.6 pJ for each 4x4 block, which corresponds to about 7.4 times less energy when compared with our proposed architecture in 90nm/nominal operating in full
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