Synthesis-for-Scan and Scan Path Ordering

Designing a scannable circuit is typically a two-step process. The circuit is first designed to meet the functional specifications, without taking the scan path into consideration. The circuit is then analyzed, and the scan path is inserted based on this analysis. When the scan path is considered during the synthesis of a circuit rather than after the synthesis, the overhead due to the scan path can be reduced. We present beneficial scan, a synthesis-for-scan technique that orders the scan path(s) during logic synthesis to maximize the amount of sharing that can take place between the functional and test logic and thereby minimize the area and performance overhead due to the scan path. We also present modifications to the state assignment algorithms to consider beneficial scan path insertion during this step. Funding: This research was supported in part by the Advanced Research Projects Agency under Contract No. DABT63-94-C-0045, and in part by the National Science Foundation under Grant No. MIP-9107760.