A Complementary GaAs 53-bit Parallel Array Floating Point Multiplier
نویسنده
چکیده
A complementary gallium-arsenide (CGaAs) 53-bit parallel array floating point multiplier is presented. The design uses Motorola's 0.5µm C-GaAs process. A conventional Wallace tree of 42 compressors is used to generate the product terms and a dynamic Ling carry select adder is utilized in the final addition to form the final mantissa. An internal latch allows the design to use a two cycle pipelined scheme. The Wallace tree has a simulated delay of 870ps and consumes about 5.2W of power. The overall clock speed is 477Mhz (limited by the final CSA adder) with a total power consumption of about 6W. Total time for just the multiply operation is 2.9ns and is faster than designs seen in the literature. The overall layout is 5.66mm x 5.98mm with over 70% of the area consumed by the Wallace tree. The design is described in detail, along with the decisions involved in the final architecture. Finally several improvements to speed and power consumption are described that will be studied in future work.
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