A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

نویسندگان

  • Andreas Hansson
  • Kees G. W. Goossens
  • Andrei Radulescu
چکیده

One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions. In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main contribution, we show how to couple path selection, mapping of cores, and channel time-slot allocation to minimize the network required to meet the constraints of the application. The time-complexity of UMARS+ is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip, reducing area by 33%, power dissipation by 35%, and worst-case latency by a factor four over a traditional waterfall approach.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Congestion estimation of router input ports in Network-on-Chip for efficient virtual allocation

Effective and congestion-aware routing is vital to the performance of network-on-chip. The efficient routing algorithm undoubtedly relies on the considered selection strategy. If the routing function returns a number of more than one permissible output ports, a selection function is exploited to choose the best output port to reduce packets latency. In this paper, we introduce a new selection s...

متن کامل

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...

متن کامل

Fault Tolerant Method to Improving Quality of Service of Be Slack Time Routing in Noc Systems

The network on chip (NoC) architectures is being proposed for implementing a routing performance on the systems for real-time multi-media applications. The Guaranteed throughput (GT) and best effort (BE) traffic on main working concept on this system. GT traffic not only lead to under-utilization of communication links and routers, but also leads to degradation of QoS parameters for BE traffic....

متن کامل

A Novel Protection Guaranteed, Quality of Transmission Aware Routing and Wavelength Assignment Algorithm for All-optical Networks

Transparent All Optical Networks carry huge traffic and any link failure can cause the loss of gigabits of data; hence protection and its guarantee becomes necessary at the time of failure. Many protection schemes were presented in the literature, but none of them speaks about protection guarantee. Also, in all optical networks, due to absence of  regeneration capabilities, the physical layer i...

متن کامل

Application Mapping onto Network-on-Chip using Bypass Channel

Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores i...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • VLSI Design

دوره 2007  شماره 

صفحات  -

تاریخ انتشار 2007