0.15μm In0.4GaAs/In0.4AlAs Metamorphic HEMT’s (M-HEMT’s) Using A Novel Triple Shaped Gate Structure Assisted By PMGI Resist

In this paper, a novel gate technology with triple shaped gate structure has proposed and developed in order to suppress unwanted gate fringing capacitance. Because high gate stem height was difficult to fabricate by means of conventional direct electron beam (E-Beam) lithography method, additional PMGI sacrificial layer was utilized in this new scheme. Increasing gate stem height as an amount of PMGI resist thickness and forming T-shaped gate structure on top of the PMGI layer, triple shaped gate structure could be finally obtained. Applying the developed technology to the fabrication to the fabrication of 0.15μm In0.4GaAs/In0.4AlAs metamorphic HEMT’s (M-HEMT’s) excellent device cutoff frequency (fT) performance of 147GHz even with 0.15μm technology has been shown owing to the remarkable reduction of gate fringing capacitance. In addition, the usage of 40% indium content in barrier layer gave rise to the improvements in Schottky gate characteristics such as gate turn-on voltage (Von) and reverse breakdown voltage (BVGD), which has important meanings in enhancement-mode operation devices. INTRODUCTION Recently, metamorphic HEMT have shown promise for high-speed and high-power applications [1]. As compared with GaAs and InP HEMT, MHEMTs with indium content of about 0.4 have advantages of high schottky barrier height (SBH) with the degradation of frequency characteristics minimized [2-3]. This high SBH property in MHEMT has special merits for enhancement-mode operation. Conventional E-mode InP HEMTs have good high speed characteristics, but the gate operating voltage is limited to about +0.5V due to the low SBH. In addition, careful consideration in parasitic effects such as gate fringing capacitance becomes more important in order to improve the device microwave performance to the utmost when shortening device minimum feature size of gate length (Lg) [4]. Generally, these phenomena are deeply correlated with the microwave characteristics such as current gain cutoff frequency (fT) and maximum oscillation frequency (fmax). This paper describes a novel fabrication technology for gate structure to suppress these parasitic effects and the performance enhancement though the developed process in enhancement-mode MHEMT with indium content of 0.4. A NOVEL TRIPLE GATE PROCESS Figure 1 shows the proposed triple shaped gate structure for the minimization of parasitic capacitance associated with gate geometry, and simulated total gate capacitance (Cg,total) with respect to the various gate stem height. Dominant factors to determine gate fringing capacitance are geometric parameters such as X and Y. Allowing that the bottom gate foot (Y) is heightened to 100nm range, the simulation results illustrate that total gate capacitance can be effectively suppressed. The process procedures for obtaining this kind of gate structure are illustrated in fig. 2. First, fine line by ebeam lithography is defined to SiO2 layer on top of PMGI/SiNx multi-layers and this pattern is transferred to the HEMT epi-layer through sequential RIE etching using O2and SF6-based plasma. On top of the obtained 0.15μm gate foot, conventional T-shaped overhang structure having bottom and top line geometry of 0.3μm and 0.8μm is defined by HI-LO-HI tri-layer resist scheme and doubleexposure-and-double-develop method. SEM images for unit process step to obtain the proposed gate structure are shown in fig. 3. Fig. 1. Simulation result for Cg,total versus Gate stem height SiN PMGI PMGI SiN PMMA PMMA Copolymer PMMA PMMA