Logic Verification in a Synthesis Environment

A new methodology for formal logic verification of combinational circuits is presented. Specifically, a structural approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural information is used to reduce the complexity of a subsequent functional method based on OBDDs. We demonstrate that OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment where many small operations are performed that modify the circuit. The experimental results show that an effective combination can be achieved between memory efficient structural methods and powerful functional methods. 1 Research reported supported in part by NSF grant MIP 94-06946 and ONR grant #N00014-92-J-1366 2 A preliminary version of this paper was presented in DAC'95 and ICCAD'93 3 Portions of this research were conducted while this author was with Institut für Theoretische Elektrotechnik, University of Hannover, Germany 4 Portions of this research were conducted while this author visited with Max-Planck-Society, Fault-Tolerant Computing Group, University of Potsdam, Germany and are based on the thesis work of S. M. Reddy at Texas A&M University.