Parasitic Engineering for Double - Gate FETs Winter 2010

Extrinsic resistance due to lateral extension doping profile can become a performance-limiter in ultrathin body Double-Gate FETs (DGFET). Historically, the intrinsic gate capacitance dominates the capacitance while the channel resistance dominates the total resistance. With devices reduced to nanometer scale, parasitic capacitances and extrinsic resistances significantly affect the device delay. For a given lateral doping gradient, the extension doping needs to be offset from the gate edge by an amount called the underlap. The current drive, and hence transistor performance, is maximized when the underlap is chosen in such a way as to balance the impact of non-abrupt doping on the short channel effects and series resistance. In this report, two-dimensional device simulations are used to study and optimize the device performance in a 50nm gate length DGFET. The silicon body thickness has been optimized to reduce DIBL and RON of the device or in other words to increase the ON/OFF current ratio of the device. The spacer thickness is optimized to pick the maximum device performance by looking at the device parasitic capacitance and extrinsic resistance. Introduction According to the ITRS Roadmap, alternative MOSFET structures are going to be needed for scaling device beyond roughly 16nm [1]. The ultrathin body Double-Gate FET (DGFET) is one of the primary candidates for replacing conventional bulk MOSFET transistors. The DGFET has been shown to have very good electrostatic gate control over the channel, enabling gate length scaling down to 10nm [1]. In these devices, the ultrathin body, whose thickness is typically 1/3 to 1/2 of the gate length, is the key to suppressing short channel effects such as Vt roll-off, drain-induced barrier lowering (DIBL), and degraded sub-threshold swing. However, it introduces an extrinsic parasitic resistance, Rs, in series with the channel and the source/drain electrodes. The effective gate overdrive is reduced by an amount Id×Rs , where Id is the drain-source current when the transistor is turned on and in saturation. This problem is quite severe in DGFET devices as the presence of two channels leads to twice the current flowing through the series resistance as compared to MOSFET devices, leading to higher potential drop across the extrinsic resistance. In this work, we use two-dimensional device simulations to engineer and optimize the effect of parasitic resistance and capacitance in a 50nm n-channel DGFET. Part I of this report is related to finding an optimum silicon thickness (Tsi) for our DGFET structure. In part II, the effect on Tspacer on threshold voltage (Vtsat) and sub-threshold slope (SS) of the DGFET is investigated. In part III, an optimal Tspacer value to achieve the highest device performance is proposed. To do so, the delay of an inverter with fan out of one is used for modeling the delay parameters. At the end of this part, we discuss the effect of a few other parameters on the device performance such as the effect of doping gradient abruptness, spacer dielectric constant variation, and raised S/D height variations. Part. I DGFET Schematic and structure: Fig. 1 illustrates the structure and doping profile of our DGFET structure for three different Tsi values. For a constant lateral doping gradient, the S/D overlap doping profiles become quite different. Electric potential profile of the channel for 5nm and 36nm DGFET structures are provided below (Fig 1b and c); the later has much higher DIBL effect and worse gate control over channel. Fig.1: DGFET Structure and Doping Profile, (a) for the nominal case Tsi=24nm, Electric potential for (b)Tsi= 5nm (c)Tsi= 36nm (a) (b) (c) To find the nominal Tsi value, we used the following scale length equation [2]: Fig 2: Scale length vs. Tsi Plugging in all the given values and using Lg/λ=1.5, we find the nominal λ=33.33nm and the nominal Tsi=24.64nm. Fig. 2 shows the plot of the above expression. To find an optimal Tsi that increases the ON/OFF currents ratio, one must consider its effect on both DIBL and RON. In order to find an optimum value for RON and DIBL, the device was simulated for various Tsi values ranging from 5nm to 40nm. According to the explanation given in the interim report, the optimum Si thickness was determined to be roughly 18nm. Fig. 3 illustrates the results. Fig 3. (a) DIBL and RON vs. Tsi ,(b) Ion and Ioff vs Tsi (a) (b) Part II. Vt and SS of the proposed DGFET as a function of Tspacer: In this part, the simulation has been done for constant optimal TSi =18.64nm determined in part I for several Tspacer values ranging from 2 to 30nm. The Id-Vg plots have been extracted for each Tspacer at constant VDS=VDD=1V. Vt_sats are calculated by using the constant current method at 10μA/W. The inverse subthreshold slope, SS, has been derived by looking at the minimum value of (∂(log Id)/ ∂Vgs) of the extracted Id-Vgs curves. The induced electric field is inversely proportional to the spacer thickness. That is, as Tspacer increases, the induced electric field from S/D to the channel decreases. Furthermore, as Tspacer increases, the S/D doping profile under the gate overlap is decreased. As a result, the gate control over channel region is improved and hence DIBL is reduced, threshold voltage is increased, and the inverse sub-threshold slope is decreased. Fig 4 and 5 show the effect of the spacer thickness on Vt and SS respectively. Fig. 6 illustrates our DGFET device with different Tspacer values. Fig 4: Vt-sat as a function of Tspacer Fig 5: SSsat as a function of Tspacer Fig 6. Simulated structure when Tspacer (a) 10nm, (b) 20nm, (c) 30nm Figure 6d provides the lateral band diagram of our DGFET device for the the following four Tspacer values: 10nm, 16nm, 20nm, and 30nm. As Tspacer decreases DIBL effect increasees. Fig 6. Lateral Band diagram: Gray: 10nm, Blue: 16nm, Red: 20nm, Green: 30nm Part III. Circuit performance, RC Delay, as a function of Tspacer: In this part we calculate the delay of an inverter with fan out of one. In Fig 7 we have shown a simple 2stage inverter. For finding the delay, this definition has been used: