Realization of Transmission-Gate Conditional-Sum [TGCS) Adders with Low Latency Time
نویسندگان
چکیده
Transmission-gate conditional-sum (TGCS) adders have been realized in a standard 2.5-pm CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32-bit addition) and consume only moderate chip area (i.e., 80x460 pm2 for 1 bit in a 32-bit adder). They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word lengths. Design and layout techniques are described in detail and experimental data are given.
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