Application of Multibit Flip-Flops by Using Carry Look Ahead Adder
نویسندگان
چکیده
The consumption of power has become an important issue in modern VLSI design. Power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. Multi-bit flip-flop is one of the methods for clock power consumption reduction. This project focuses on reduction of power using multi-bit flipflops by clock synchronization. Two single bit flip-flops are synchronized with one clock pulse or clock edge which reduces power consumption. Merging single bit flip-flops into one multi-bit flip-flop avoids duplicate inverters, lowers the total clock power consumption and reduces the total area. A combination table which can store the flip-flops that can be merged to obtain a multi-bit flip-flop. This project focuses on D flip-flop which increases the loading of the clock signal. QCL adder is used as an application for multibit flip-flop. Highest ‘1’ bit finding algorithm is used to find the highest 1 bit from the output of QCL adder. This algorithm checks the output of QCL adder in each cycle.
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