Design and verification of a CAN controller for custom ASIC
نویسندگان
چکیده
This paper presents a novel architecture and verification model of the CAN protocol controller for ASIC implementation. The key features of the proposed CAN controller are flexibility in terms of interfacing with host processors and smaller chip size. Also, the architecture is efficient for Intellectual Property (IP) reuse because of its flexibility and synthesis efficiency. For verification of the designed controller, we developed a verification model for fast verification during the design phase. The gate counts of the core logics in the proposed CAN controller are 3189 gates which are much smaller than other controllers. After successful verification, the CAN controller was fabricated by using 0.35_CMOS process.
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