Distributed Arithmetic Unit Design for Fir Filter
نویسندگان
چکیده
In this paper different distributed Arithmetic (DA) architectures are proposed for Finite Impulse Response (FIR) filter. FIR filter is the main part of the Digital Signal Processing. In Digital Signal Processing we can use Multiply Accumulator Circuit (MAC) and DA for filter design.MAC consumes more power and area because of multiplier and adder circuit. The design distributed arithmetic is run time reconfigurable. The implementation results are provided to demonstrate a high speed and low power architectures. The different DA architecture are implemented in verilog and verified via simulation. In the 16-tap FIR filter design of distributed arithmetic gives better results, 50% of power dissipation and area can be achieved by LUT less2 architecture. 49% of delay can be achieved by separated LUT DA architecture.
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