Modeling and behavioral simulation of noise transfer characteristics of a 2 GHz phased - locked loop for frequency synthesizer

نویسندگان

  • K. Kalita
  • T. Bezboruah
چکیده

We present here an analytical phase noise model of phased-locked loop for frequency synthesizer and its simulation in GHz frequency range. The noise model has been derived and simulated considering two different filter sections in the loop of the phased-locked loop model, namely: (i) active lag-lead filter and (ii) standard feedback approach. The noise transfer functions of the phased-locked loop frequency synthesizer are derived in s-domain for analysis. The mathematical model and analysis for the five main noise transfer functions which are existed in the system have been derived for analysis. The simulation of the phase noise is performed by using MATLAB (Version: 7.1). Here we will discuss in details the procedure for mathematical derivation of the noise model for both active leg-lead filter and filter with standard feedback approach in the loop, its simulation and their results.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A-New-Closed-form-Mathematical-Approach-to-Achieve Minimum Phase Noise in Frequency Synthesizers

The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase ...

متن کامل

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...

متن کامل

Switchable PLL Frequency Synthesizer andHot Carrier Effects

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz ...

متن کامل

Hardware Description Language Design of Σ-Δ Fractional-N Phase-Locked Loop for Wireless Applications

This paper discusses a systematic design of a ∑-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of di...

متن کامل

Behavioural Modelling and Simulation of PLL Based Integer N Frequency Synthesizer using Simulink

Behavioural modeling and simulation of a PLL based integer n frequency synthesizer has been illustrated in this paper. The synthesizer generates a signal of 5.15-5.25 GHz in the UNII (Unlicensed National Information Infrastructure) lower band which is used by IEEE 802.11(a). All the PLL building blocks are modeled and simulated using Simulink. The PLL performance has been evaluated using MATLAB...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2011