Reduced Power Dissipation Through Truncated Multiplication

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signi cantly reduced by a technique known as truncated multiplication. With this technique, the least signi cant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most signi cant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits. 1: Introduction High-speed parallel multipliers are fundamental building blocks in digital signal processing systems [1]. In many cases, parallel multipliers contribute signi cantly to the overall power dissipation of these systems [2]. As transistor counts, clock frequencies, and the desire for portability increase, so does the need for low-power parallel multipliers. Parallel multipliers are typically implemented as either array multipliers [3], [4] or tree multipliers [5] [7]. For both types of parallel multipliers, Booth-encoding can be employed to reduce the number of partial products [8], [9]. Estimates given in [10] [12] indicate that array multipliers dissipate more power than tree multipliers and that Booth-encoded multipliers dissipate more power than multipliers that are not Booth-encoded. Various techniques have been developed to reduce the power dissipation of parallel multipliers. Several of these techniques reduce power dissipation by eliminating spurious transitions [13] [15]. Other research has focused on developing novel multiplier architectures and sign-extension techniques to reduce power dissipation and improve performance [16] [19]. Another approach is to develop low-power 3-2 counters and 4-2 compressors, which are key components in parallel multipliers [20] [22]. Although each of these techniques helps reduce power dissipation, further reductions will be needed for future digital signal processing systems. This paper examines reductions in power dissipation that can be achieved through the use of truncated multiplication. Sections 2 gives an overview of truncated multipliers, and Section 3 discusses their implementation. Section 4 compares the power dissipation, delay, and area of truncated multipliers to standard parallel multipliers. Section 5 gives conclusions. 2: Truncated multipliers In the discussion to follow, it is assumed that an unsigned n-bit multiplicand A is multiplied by an unsigned n-bit multiplier B to produce an unsigned 2n-bit product P . For fractional numbers, the values for A, B, and P are A = n 1 X i=0 ai2 n+i B = n 1 X i=0 bi2 n+i P = 2n 1 X i=0 pi2 2n+i (1) The multiplication matrix for P = A B is shown in Figure 1a. For most high-speed applications, parallel multipliers are used to produce the product. In many computer systems, the 2n-bit products produced by the parallel multipliers are rounded to n bits to avoid growth in word size. As presented in [23] [26], truncated multiplication provides an e cient method for reducing the hardware requirements of rounded parallel multipliers. With truncated multiplication, only the n + k most signi cant columns of the multiplication matrix are used to compute the product. The error produced by omitting the n k least signi cant columns and rounding the nal result to n bits is estimated, and this estimate is added with the n+ k most signi cant columns to produce the rounded product. Although this leads to additional error in the rounded product, various techniques have been developed to help limit this error. With the Constant Correction Truncated Multiplier presented in [24], a constant is added to columns n 1 to n k of the multiplication matrix. The constant helps compensate for the error introduced by omitting the n k least signi cant columns (called reduction error), and the error due to rounding the product to n bits (called rounding error). The expected value of the sum of these error Etotal is computed by assuming that each bit in A, B and P has an equal probability of being one or zero. As described in [24], this gives Etotal = 0:25 n k 1 X i=0 (i+ 1)2 2n+i 2 n (1 2 ) (2) The constant Ctotal is obtained by rounding Etotal to n+ k fractional bits, such that Ctotal = round(2Etotal) 2 (3) where round(x) indicates that x is rounded to the nearest integer. The multiplication matrix for a truncated multiplier that uses this method is shown in Figure 1b. In [26], the Variable Correction Truncated Multiplier is introduced. With this type of multiplier, the values of the partial product bits in column n k 1 are used to estimate the error due to leaving o the n k least signi cant columns. This is accomplished by adding the partial products bits in column n k 1 to column n k. To compensate for the rounding error that occurs when truncating the products bits in columns n 1 to n k, a rounding constant, Cround, is added to the multiplication matrix. Since each product bit has an equal probability of being one or zero and the rounding constant cannot go beyond column n k, the value used for Cround is Cround = 2 n (1 2 ) (4) which corresponds to the additive inverse of the expected value of the rounding error, truncated after column n k. The correction constant is added by putting ones in columns n 2 to n k, as shown in Figure 1c. Compared to Constant Correction Truncated Multipliers, Variable Correction Truncated Multipliers have less average, mean square and maximum error for given values of n and k, but require more hardware. As discussed in [27], array multipliers can be implemented more e ciently as Variable Correction Truncated Multipliers and tree multipliers can be implemented more e ciently as Constant Correction Truncated Multipliers.