Modelling multiprocessor systems in PEPA

The model is inspired from [2] (see also [1, 3]). Consider a multiprocessor system with a shared memory. Processes running on this system have to compete for access to the common memory: to gain access and to use the common memory they need also to acquire the system bus which is released when access to the common memory is terminated; for simplicity the bus will not be explicitly represented in the following. Processes are mapped onto processors. The processors are not explicitly represented but they determine the rate of activities in the associated processes, i.e. all processes have the same functional behaviour, but actions progress at different speeds depending on the processor on which they are running, and the number of processes present on the processor. It is the modeller’s responsibility to select rates appropriately. A protocol which is not completely fair, but simply prevents one processor from monopolising the memory, imposes that after each access of a processor to the memory, some other processor must gain access before the first can access again. A process running on the ith processor is represented as Pi: