Delay Analysis of neuron-MOS and Capacitive Threshold- Logic
نویسندگان
چکیده
A model for the delay of neuron-MOS (neuMOS) and Capacitive Threshold-Logic (CTL) based logic circuits is presented for the first time. It is based on the analysis of the basic neuron-MOS [l] and CTL gate structures [a]. A closed form analytic expression for the delay of the threshold gate is derived. A relation for the delay in terms of an ordinary CMOS inverter delay expressed as a function of the number of inputs to the threshold gate is presented. This relation is shown to be useful in comparing the delay of logic circuit designs based on neu-MOS or CTL and ordinary CMOS. Keuwodsneuron-MOS, capacitivethreshold logic, floating gate transistor
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