Probabilistic representation and manipulation of Boolean functions using free Boolean diagrams

The advent of increasingly dense and fast Very Large Scale Integrated (VLSI) circuits allows for the design of larger and more sophisticated digital logic circuits. Efficient logic representations are necessary for the synthesis, testing and verification of these circuits. This thesis introduces a new logic representation, called the Free Boolean Diagram (FBD). This representation can be manipulated in time comparable to existing methods and the complexity of the representation for a number of circuit classes is provably more efficient than existing representations such as the Reduced Ordered Binary Decision Diagram (ROBDD). Free Boolean Diagrams allow for function vertices that represent Boolean and, or and exclusive-or, in addition to the decision vertices found in conventional Binary Decision Diagrams. A previous result is extended to probabilistically determine the equivalence of Free Boolean Diagrams in polynomial time. A strongly canonical form is maintained for Free Boolean Diagrams using "signatures". New algorithms for the probabilistic construction of Free Boolean Diagrams from multilevel combinational logic circuits and the manipulation of these graphs are developed and implemented in a software package. The results of the application of the package to combinational logic verification and Boolean satisfiability problems are presented. Thesis supervisor: Srinivas Devadas Title: Associate Professor of Electrical Engineering and Computer Science