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Shifting the design entry point up to the system-level is the most important countermeasure adopted to manage the increasing complexity of Multiprocessor System on Chip (MPSoC). The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of power and energy efficiency. However, taking decisions at this level is very difficult, since the design space is extremely wide and it has so far been mostly a manual activity. Efficient system-level power estimation tools are therefore necessary to enable proper Design Space Exploration (DSE) based on power/energy and timing. In this thesis, we propose a tool based on efficient hybrid system-level power estimation methodology for MPSoC. In this methodology, a combination of Functional Level Power Analysis (FLPA) and system-level simulation technique are used to compute the power of the whole system. Basically, the FLPA concept is proposed for processor architecture in order to obtain parametrized arithmetic power models depending on the consumption of the main functional blocks. In this work, FLPA is extended to set up generic power models for the different parts of the platform. In addition, a simulation framework is developed at the transactional level to evaluate accurately the activities used in the related power models. The combination of the above two parts leads to a hybrid power estimation that gives a better trade-off between accuracy and speed. The proposed methodology has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed methodology is also scalable for exploring complex emJanuary 12, 2013 Santhosh Kumar Rethinagiri Page vi bedded architectures. Based on the proposed methodology, our Power Estimation Tool at System-Level (PETS) is developed. The effectiveness of our PETS tool is validated in terms of accuracy and speed through a typical mono-processor and multiprocessor embedded system designed around the TI OMAP (3530 and 5912) and the Xilinx Virtex II Pro FPGA boards. This methodology is demonstrated and evaluated by using a variety of basic programs to a complete media benchmarks. In order to ensure accuracy and speed, first we compared the estimated power value with the real board measurements for both mono-processor and multiprocessor architectures. Our obtained power estimation results provide less than 3% of error for mono-processor, 3.8% for homogeneous multiprocessor system and 4.3% for heterogeneous multiprocessor system. Second, we compared the estimation speed of our tool with the state-of-the-art power estimation tools and it resulted up to 70x faster. January 12, 2013 Santhosh Kumar Rethinagiri Page vii