Hardware Optimazation of Viterbi Decoder
نویسندگان
چکیده
This paper describes the design and optimization of Viterbi Decoder used for (2,1,3) convolution code. It first introduces the basic principle of Viterbi Algorithm, then describes the basic circuit architecture of the Viterbi Decoder. Then it compares several different architecture and circuit optimization method, which emphasize on aspects such as throughput, power and memory consumption. Finally it concludes the result and gives some suggestion on the design. Keywords-Viterbi Algorithm; Architecture; Trace Back; Register Exchange;Optimization
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