Method for Automatic Generation of Rtl in Vhdl Using Decision Diagrams

In recent years, decision diagrams have earned a prominent place in the field of logic design as means of efficient representation of switching function, in terms of needed storage space and processing complexity, especially for the tasks of design, testing and verification of logic circuits. In this paper, we focus on a XML based system for description of the structure of decision diagrams with special attention on its application in high-level synthesis, automatization of design of logic networks. The system we propose is capable of automatically producing hardware description, RTL models in VHDL. It uses XML for description of decision diagrams and a set of XSLT based scripts for conversion of decision diagrams to VHDL hardware model. VHDL is a well established industrial standard in this area and the RTL models produced by in this way can be synthesized using commercial logic synthesis tools. This feature permits fast prototyping and much quicker experimentation regarding decision diagrams in the fields of logic synthesis and circuit testing. It also enables our framework to take the central role in much wider scope connecting various other software packages that deal with decision diagrams on some level with industrial standard simulation and synthesis software.