Systolic FIR filter Based FPGA
نویسنده
چکیده
In this paper, we first review in detail the basic building blocks of reconfigurable devices, essentially, the fieldprogrammable gate arrays (FPGAs), then we describes a highspeed, reconfigurable, Systolic FIR filter design implemented in the Virtex-II series of FPGAs. The VHDL description of this filter is used for simulation and EDIF for implementation using Xilinx's place and route tools. The VHDL simulation shows that the filter behaves as expected
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