Performance Evaluation of a Bufferless N x N Synchronous Clos ATM Switch with Priorities and Space Preemption
نویسندگان
چکیده
We consider a synchronized bufferless Clos ATM switch with input cell processor queues. The arrival process to each input port of the switch is assumed to be bursty and it is modeled by an Interrupted Bernoulli Process. Two classes of cells are considered. Service in an input cell processor queue is head-of-the-line without preemption. In addition, space preemption is used. That is, a high priority cell arriving at a full queue takes the space occupied by the low priority cell with the least waiting time in the queue but not the one in service. Each cell processor queue is modeled as a priority IBP/Geo/l/K+l queue with space preemption. We present an exact analysis of the priority queue.The results obtained are then used in an approximation algorithm for the analysis of the ATM switch. "Supported in part by DARPA under grant no. DAEA18-90-c-0039.
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An Approximate Analysis of a Bufferless N x N Synchronous Clos ATM Switch
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