Con guration Cloning: Exploiting Regularity in Dynamic DSP Architectures

Existing FPGAs have fairly simple and ine cient con guration mechanisms due to the relative infrequency of recon guration. However a large class of dynamically con gurable architectures for DSP and communications can bene t from special-purpose con guration mechanisms which allow signi cant savings in con guration speed, power and memory. Light weight con guration mechanisms allow much ner grained dynamic recon guration techniques of DSP and communications functions that tune algorithm and architecture parameters incrementally to track data and environment variations. These adaptive techniques exploit the time-varying nature of many DSP applications and avoid the power costs associated with worst-case design. In this paper we develop a new FPGA con guration method called con guration cloning from the analogy of biological cloning. The main motivation behind con guration cloning is to exploit spatial and temporal regularity and locality in algorithms and architectures by copying and operating on the con guration bit-stream already resident in an FPGA. This results in a speed and power improvement over o -chip partial recon guration techniques but does require additional interconnects and control hardware on the FPGA. But in contrast to multiple-context and striped con guration approaches, cloning requires only a small amount of hardware overhead to greatly increase the on-chip con guration bandwidth. Details of the con guration cloning mechanism are described. Two familiar DSP applications, motion estimation and FIR ltering, are explained to demonstrate order of magnitude reductions in con guration time and power compared to existing con guration techniques. Resource recycling is also presented as a generic method of reclaiming freed up logic resources and using them as local memory to greatly reduce I/O requirements.