ACETM Automated Circuit Extraction

This paper provides an introduction to ACETM Automated Circuit Extraction technology from Applied Wave Research, Inc. (AWR®). ACETM is an innovative approach to avoid the over dependence of EM analysis as a design tool. The ACETM software automates the modeling of complex interconnect structures defined as paths by assembling their equivalent electrical models on-the-fly using the very same network representation designers themselves would make use of if they had the time and patience to do so. The simulation of the equivalent circuit is done in a fraction of the time that it would take EM tools to create equivalent S-parameters. The speed, accuracy, and parametric nature of ACETM software enable engineers to return to real design by exploring design alternatives and changes in seconds. Obviously, EM verification is still a necessary part of the flow, but the ACETM tool enables engineers to design once again rather than analyze after the event, even on many of the most challenging RF and MW designs. Introduction Today’s traditional approach to RF and/or Microwave circuit design is being pressured simultaneously by an increase in operating frequencies and bandwidth and a decrease in physical footprint size. The result is that the physical design challenges faced by these designers are rapidly increasing, while choices for how these challenges should be best addressed are not. The drive to put more functionality into the same or smaller space is particularly demanding on the RF/Microwave design flow because of the increased and unavoidable need to model interconnects and their interactions. Ideally, modeling all of the interactions at the schematic level using distributed line, discontinuity, coupled-line models and vias is preferred. While there is nothing preventing an engineer from doing this, the complexity of modern wireless designs makes this an unrealistic and unreasonable approach at a schematic level, given that this manual process is incredibly time consuming and error prone. Figure 1 shows a very simple section of PCB multi-layer interconnects, minus the SMT components ! Figure 1: Simple section of PCB multi-layer interconnect showing coupled line structure with bend discontinuities and via holes W1