High performance zero-crossing based pipelined analog-to-digital converters

As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow for more power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology have made analog design more difficult. More specifically, the design of a high gain op-amp, a fundamental analog building block, has become more difficult in scaled processes. In this work, op-amps in pipelined ADCs are replaced with zero-crossing detectors(ZCD). Without the closed-loop feedback provided by the op-amp, a new set of design constraints for Zero-Crossing Based Circuits (ZCBC) is explored. Thesis Supervisor: Hae-Seung Lee Title: Professor