Design & study of a low power high speed full adder using GDI multiplexer
نویسندگان
چکیده
The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multiplexers. Full adder is a very common example of combinational circuits and is used widely in Application Specific Integrated Circuits (ASICs). It is always advantageous to have low power action for the sub components used in VLSI chips. The explored technique of realization achieves a low power high speed design for a widely used subcomponentfull adder. Simulated outcome using state of-art simulation tool shows finer behavioral performance of the projected method over general CMOS based full adder. Power, speed and area comparison between conventional and proposed full adder is also presented.
منابع مشابه
Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input
The low power techniques are becoming more important due to rapid development of portable digital applications; demand for high-speed and low power consumption.GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. The basic cell of GDI consists of two transistors where three terminals i.e Gate, Sourc...
متن کاملA Design of Low Power Low Area High Speed Full Adder Using GDI Technique
Full Adder is the basic building block for various arithmetic circuits such as compressors, multipliers, comparators and so on. 1-bit Full Adder cell is the important and basic block of an arithmetic unit of a system. Hence in order to improve the performance of the digital computer system one must improve the basic 1-bit full adder cell. In this, Full Adder is designed by using Hybrid-CMOS log...
متن کاملEvaluation of Power Delay Product for Low Power Full Adder Circuits based on GDI Logic Cell using Mentor Graphics
This paper presents high speed and low power full adder cells designed with an alternative internal logic structure and Gate Diffusion Input (GDI) logic styles and hybrid CMOS logic style that lead to have a reduced Power Delay Product (PDP). The main design objective for this adder module is not only providing low-power dissipation and high speed but also full-voltage swing. In the first desig...
متن کاملDesign and Analysis of GDI Based Full Adder Circuit for Low Power Applications
Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units. Due to scaling trends and portability of electronic devices there is a high demand and need for low power and high speed digital circuits with small silicon area. So, design and a...
متن کاملEfficient Design of Low Power ALU using PTL-GDI Logic Full Adder
In this paper, we proposed a low power 1-bit full adder (FA) with 10-transistors and this is used in the design ALU. 16-bit ALUs are designed and compared with the existing design. The proposed design consists of PTL-GDI adder and mux circuits. By using low power 1-bit full adder in the implementation of ALU, the power and area are greatly reduced to more than 50% compared to conventional desig...
متن کامل