Design of a Real-time Hough Transform on Configurable Logic

The Hough transform (HT) is frequently used to locate possibly occluded straight edges or lines in machine vision. Each detected edge pixel in a binary image votes for a potential edge upon which it might lie. The HT is potentially suitable for video-rate applications such as motion detection (by comparison of successive HT transformed frames), but the computational burden is high, motivating hardware implementations. There have been a number of HT implementations using the CORDIC algorithm which allows trigonometric angles to be generated primarily by shifts and additions and which can be adapted to find HT radii. However, CORDIC generates a series of converging micro-rotations, whereas we have found that a series of angles can be swept out, thus further increasing the throughput, which is still slow in traditional CORDIC. By dividing up the angle range, our method can incrementally improve the angular resolution and accuracy, without the need for scaling factors and with uni-directional rotations. The successful implementation was achieved on an XC2V3000 Virtex-2, which is one of the large capacity SRAM-based platform FPGAs from Xilinx. The Handel-C hardware compiler running within Celoxica’s DK2/3 IDE was used to develop the design on an RC203 board. The RC203 board is one of Celoxica’s range of development boards, while a low-cost version for educational usage, the RC101 has recently been released. (The alternative Digilent XUP V2P ”Curriculum on a Chip” also comes into contention.2) In fact, early work on the real-time HT took place on a low-cost Digilent board, before transferring to an RC1000-PP (Virtex 1), and, thence, the Handel-C code was ported to the RC203 system. Handel-C uses hardware templates to model program constructs and, hence, there has been a concern over resource usage. In fact, the compiled design used less than 7% of the Virtex-2 (1,113 slices) and ran at 50 MHz. If the angle range is divided into two, then the real-time HT accomplishes 26 frame/s operating on 256 × 256 pixel images at an angular resolution of 0.9. Accuracy improves as the angle range is successively divided up, but even without division, the error is only a few per cent, sufficient for typical applications. Currently, on-chip block RAM is utilized to store the vote arrays (divided into sectors to allow concurrent access). However, as this resource is limited quantization of the votes will become necessary for scaled-up designs.