Design and Verification of Low Power SRAM using 8T SRAM Cell Approach

SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high integration and fast performance. Lowering power consumption and increasing noise margin have become two central topics in every state of SRAM designs.The Conventional 6T SRAM cell is very much prone to noise during read operation. To overcome the read SNM problem in 6T SRAM cell, researchers have considered different configurations for SRAM cells such as 8T, 9T, 10T etc. bitcell design. These designs can improve the cell stability but suffer from bitline leakage noise. This paper targets reduction of power consumption and evaluates the static noise margin of 8T SRAM bitcells. In this paper, we propose a novel 8T SRAM topology that achieves both cell stability and also reduces Power Consumption. With the proposed 8T SRAM circuit, the Read Static Noise Margin is nearly twice that of the Conventional 6T SRAM Cell. General Terms CMOS logic, SRAM and VLSI.