VLSI Implementation of a Modified Efficient SPIHT Encoder
نویسندگان
چکیده
Set Partitioning in Hierarchical Trees (SPIHT) is a highly efficient technique for compressing Discrete Wavelet Transform (DWT) decomposed images. Though its compression efficiency is a little less famous than Embedded Block Coding with Optimized Truncation (EBCOT) adopted by JPEG2000, SPIHT has a straight forward coding procedure and requires no tables. These make SPIHT a more appropriate algorithm for lower cost hardware implementation. In this paper, a modified SPIHT algorithm is presented. The modifications include a simplification of coefficient scanning process, a 1-D addressing method instead of the original 2-D arrangement of wavelet coefficients, and a fixed memory allocation for the data lists instead of a dynamic allocation approach required in the original SPIHT. Although the distortion is slightly increased, it facilitates an extremely fast throughput and easier hardware implementation. The VLSI implementation demonstrates that the proposed design can encode a CIF (352 × 288) 4:2:0 image sequence with at least 30 frames per second at 100-MHz working frequency. key words: discrete wavelet transform (DWT), set partitioning in hierarchical trees (SPIHT), image coding
منابع مشابه
Efficient Architecture for SPIHT Algorithm in Image Compression
A arithmetic coder architecture with a high throughput memory efficient for set partitioning in hierarchical trees is proposed in this paper. This paper also presents a throughput efficient image compression using ‘Set Partitioning in Hierarchical Trees’ (SPIHT) algorithm for compression of images. The SPIHT use inherent redundancy among wavelet coefficients and suited for both gray and color i...
متن کاملAn Efficient Vlsi Implementation for the Soft Information-set Decoding Algorithm
Error-correcting codes are present in basically all modern data communications and data storage systems. When top-performance is required, the corresponding algorithms (encoder + decoder) are implemented in hardware. This paper describes a VLSI implementation for an information-set-based error correcting decoder. More specifically, we present the modified Gauss-Jordan elimination block, which c...
متن کاملPerformance and Analysis of Video Compression Using SPIHT Algorithm
Ubiquitous use of real-time video communication on the Internet requires adaptive applications that can provide different levels of quality depending on the amount of resources available. For video coding this means that the algorithms must be designed to be efficient in bandwidth usage, processing requirements and quality of the reconstructed signal. Of most algorithms developed, SPIHT algorit...
متن کاملA Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture beco...
متن کاملAn Efficient VLSI Implementation of Lossless ECG Encoder Design
An efficient VLSI implementation of a lossless electrocardiogram encoding circuit is designed for remote monitoring service. To reduce the wireless transmission power and the amount of storage data, an efficient lossless encoding algorithm had been built for the ECG signal compression. This algorithm consists of an adaptive predictor and a two-stage entropy encoder. The VLSI architecture of thi...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- IEICE Transactions
دوره 89-A شماره
صفحات -
تاریخ انتشار 2006