Design of 16-bit Carry Save Adder using Constant Delay Logic Style
نویسندگان
چکیده
Addition is one of the vital parts of any electronic system design because every electronic system needs this basic operation. Researchers have done a lot of work on various adders to optimise their performance. So, they found that Carry Save adder is best in terms of delay calculation and power consumption. That is why this proposed work use this adder. This paper is primarily focus on design of 16-bit carry save adder using constant delay logic style. This research article primarily focuses on design and simulation of Constant Delay (CD) based buffer and Carry Save adder. Tool used for this 16-bit design work is Tanner EDA v13 and technology used is 180nm and 32nm and compare parameters on these technologies. Keywords-CD logic buffer design, CARRY section and SUM section of Full Adder, 16-bit Carry Save adder.
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